1. Field of the Invention
The present invention relates generally to dynamic-type memory cells and more particularly to dynamic-type memory cells employing substrate isolation to increase cell density. The invention also relates to a method of making such cells.
2. Description of the Prior Art
Conventionally, a demand for a high degree of integration of semiconductor devices or VLSI has been met mainly with a technique of fine structure of semiconductor devices. Recently, however, a limit thereto is approaching and there is an active movement to realize a higher degree of densification by improving the structure of semiconductor devices as well as by expecting a breakthrough in lithography technique.
FIGS. 1 and 2 are schematic block diagrams of a conventional MOS dynamic RAM.
First, referring to FIGS. 1 and 2, the whole structure of the conventional MOS dynamic RAM is described. A row address signal is stored in a row address buffer 61. The row address signal stored in the row address buffer 61 is applied to a row decoder 62 and decoded so that the row direction of a memory cell array 63 is addressed. On the other hand, a column address signal is stored in a column address buffer 67 and the column address signal is decoded by a column decoder 66 and applied to the memory cell array 63 through a sense amplifier 65, with the result that the column address of the memory cell array 63 is specified.
An I/O circuit 68 is connected to the sense amplifier 65 and the input and output of the I/O circuit 68 is switched by an input and output control circuit 64. That is, when the I/O circuit 68 is switched on the input side, inputted data is stored in addressed and predetermined memory cells in the memory cell array 63 through the sense amplifier 65. When the I/O circuit 68 is switched on the output side, data is read from addressed and predetermined memory cells and outputted from the sense amplifier 65 through the I/O circuit 68. The memory cell array 63 comprises n.times.m memory cells and each memory cell is connected to a word line and bit line as shown in FIG. 2.
FIGS. 3 and 4 are a plan view and a sectional view, respectively, of a cross point cell proposed as a so-called ultimate feature of a fundamental cell of a dynamic RAM which is a leading example of such a high degree of integration, in which as a switching transistor a vertical transistor is employed using as a channel region the wall surface of a hole formed on a silicon substrate.
An example of the above mentioned cross point cell is disclosed in ISSCC 86 Lecture No. FAM 19.5. February, 1986, by A. H. Shah, et al.
Referring to FIGS. 3 and 4, numeral 1 denotes an n.sup.+ diffused layer serving as a drain and a bit line, numeral 2 denotes a polycrystal silicon serving as a word line, numeral 3 denotes a groove, numeral 4 denotes an isolating oxide film, numeral 5 denotes a channel portion of a switching transistor, numeral 6 denotes a gate oxide film, numeral 7 denotes a buried contact serving as a source, numeral 8 denotes a polycrystal silicon memory electrode, numeral 9 denotes a capacitor oxide film, numeral 10 denotes a gate electrode, and numeral 11 denotes a p.sup.+ substrate. The dimensions are W1=2.6 .mu.m and W2=3.4 .mu.m.
The manufacturing process thereof is now described to show problems of the thus structured semiconductor memory device as shown in FIGS. 5A to 5E. Referring to FIG. 5A, numeral 11 denotes a p-type substrate of high concentration, numeral 12 denotes a p-type (100) epitaxial growth layer of low concentration, numeral 13 denotes an n-type diffusion layer of high concentration formed by an ion implantation process, numeral 14 denotes a field isolating oxide film, numeral 15 denotes a groove formed by reactive ion etching, and numeral 16 denotes a thin gate oxide film (SiO.sub.2) of 15 nm in thickness.
Referring to FIG. 5B, the groove 15 has been filled to the top with an n.sup.+ polycrystal silicon 171 and then partially removed by etching to the depth as shown, the oxide film 16 is thereafter etched from the top, so that a gap 18 which has been etched slightly deeper than the surface of the polycrystal silicon 171 is formed.
As shown in FIG. 5C, a polycrystal silicon layer 172 is then deposited on the polycrystal silicon 171 having the above-mentioned gap 18 and the gap 18 between the polycrystal silicon 171 and the wall is filled up.
In addition, as shown in FIG. 5D, the polycrystal silicon layer 172 on the polycrystal silicon 171, a wall of the groove 15, the n-type diffused layer 13 of a high concentration and the field isolating oxide film is removed by an anisotropic etching process. As a result, the polycrystal silicon film 172 is filled in the gap 18 between the above-mentioned polycrystal silicon 171 and the wall.
Finally, as shown in FIG. 5E, a semiconductor memory device including a vertical MOS transistor and a vertical capacitor is formed by forming a gate oxide film 19 and a gate electrode 20.
Now problems involved in the structure and the manufacturing process of the above-mentioned semiconductor memory device will be described. In the above-mentioned semiconductor memory device, the step between the surface of the buried polycrystal silicon 171 and the major surface becomes a channel length 36 of a vertical MOS transistor as shown in FIG. 5E, and the etching of the polycrystal silicon 171 must be controlled very precisely.
In addition, the doping of the channel region is affected substantially by autodoping as a result of a tendency of ions to migrate from the more heavily doped layer 11 to layer 12.
In addition, since wall surfaces tend to have different crystal orientations forming the channel regions, non-uniformity of the threshold voltage is caused. Furthermore, a thin polycrystal silicon is deposited and, after the n.sup.+ polycrystal silicon 171 and wall surfaces are buried, plasma etching is performed with CF.sub.4. This plasma etching induces crystal defects in the semiconductor surface which forms a channel, tending to degrade all transistor characteristics.
In addition, if an interval of each memory cell is shortened in the above-mentioned MOS dynamic RAM, an electric charge leaks from transistor of one memory cell to a capacitor for storage of the other memory cell and, as a result, malfunction is caused.